Datasheet
ECU
Module
DS90UB914Q
DS90UB913Q
DIN[11:0]
, HS, VS,
PCLK
CMOS
Image
Sensor
I
2
C
I
2
C
SDA
SCL
SDA
SCL
PC
DES B: ID[x](0xC2)
SLAVE_ID2_MATCH(0xA4)
SLAVE_ID2_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA6)
SLAVE_ID2_INDEX(0xA2)
DS90UB914Q
DS90UB913Q
CMOS
Image
Sensor
I
2
C
I
2
C
SDA
SCL
SDA
SCL
Camera B
Slave ID: (0xA0)
SER A: ID[x](0xB0)
DES A: ID[x](0xC0)
SLAVE_ID1_MATCH(0xA0)
SLAVE_ID1_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA2)
SLAVE_ID2_INDEX(0xA2)
Camera A
Slave ID: (0xA0)
Master
SER B: ID[x](0xB2)
Slave ID: (0xA2)
Slave ID: (0xA2)
PC/
EEPROM
PC/
EEPROM
ROUT[11:0],
HS, VS,
PCLK
DIN[11:0]
, HS, VS,
PCLK
ROUT[11:0],
HS, VS,
PCLK
DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B –JULY 2012–REVISED APRIL 2013
Figure 36. Multiple Device Addressing
Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the birectional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25µs.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
See Figure 37 for an example of this function.
The maximum time (t1) between the rising edge of GPIO (i.e. sync signal) arriving at Camera A and Camera B is
25µs.
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