Datasheet

HOST DS90UB914Q
SCL
SDA
RPU RPU
10k
R
ID0
SCL
SDA
To other
Devices
IDx[0]
1.8V
V
DDIO
10k
R
ID1
1.8V
IDx[1]
DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Figure 35. ID[x[ Address Decoder on the Deserializer
Table 8. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q Deserializer
ID[x] Resistor Value — DS90UB913Q Serializer
Resistor RID1 Ω Resistor RID0 Ω Address 7'b Address 8'b 0 appended
(1%Tolerance) (1%Tolerance) (WRITE)
0k 0k 0x60 0xC0
0k 3k 0x61 0xC2
0k 11k 0x62 0xC4
0k 100k 0x63 0xC6
3k 0k 0x64 0xC8
3k 3k 0x65 0xCA
3k 11k 0x66 0XCC
3k 100k 0x67 0XCE
11k 0k 0x68 0XD0
11k 3k 0x69 0XD2
11k 11k 0x6A 0XD4
11k 100k 0x6B 0XD6
100k 0k 0x6C 0XD8
100k 3k 0x6D 0XDA
100k 11k 0x6E 0XDC
100k 100k 0x6F 0XDE
Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input and LOCK is TRI-
STATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q completes its lock
sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered
from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on
the OEN and OSS_SEL setting (Table 5). See Figure 19.
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