Datasheet

SDA
SCL
S P
START condition, or
START repeat condition
STOP condition
SCL
SDA
START
STOP
1 2 6 7
8
9
1 2
8
9
MSB
7-bit Slave Address
R/W
Direction
Bit
Acknowledge
from the Device
MSB
Data Byte
*Acknowledge
or Not-ACK
ACK N/ACK
Repeated for the Lower Data Byte
and Additional Data Transfers
LSB LSB
Bus Activity:
Master
SDA Line
Bus Activity:
Slave
Start
Slave
Address
A
C
K
S
Address
A
C
K
S
Start
Slave
Address
A
C
K
N
A
C
K
P
Stop
Data
0 1
Register
7-bit Address 7-bit Address
A
C
K
A
C
K
A
C
K
S
P
Stop
Bus Activity:
Slave
SDA Line
Bus Activity:
Master
Slave
Address
Address Data
Start
0
Register
7-bit Address
DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Figure 29. Write Byte
Figure 30. Read Byte
Figure 31. Basic Operation
Figure 32. Start and Stop Conditions
Slave Clock Stretching
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control To communicate and synchronize with remote
devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913/914Q chipset.
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