Datasheet

DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
DS90UB913Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name Pin No. I/O, Type Description
GPO[3]/CLKIN 18 Input/Output, GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
LVCMOS on the Deserializer or can be configured to be the output of the local register setting
on the Serializer. It can also be configured to be the input clock pin when the
DS90UB913Q Serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB913/914Q chipsets
working with an external oscillator.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 4
Open Drain SCL requires an external pull-up resistor to V
DDIO
.
Input/Output, Data line for the bidirectional control bus communication
SDA 5
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
Device mode select
Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can be
MODE 8
w/ pull down used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 5
Device ID Address Select
ID[x] 6 Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor to
Ground and 10 kΩ pull-up to 1.8V rail. See Table 7
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB 9 PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
RES 7
w/ pull down This pin MUST be tied LOW.
FPD–Link III INTERFACE
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect
DOUT+ 13
CML must be AC Coupled with a 100 nF capacitor.
DOUT- 12 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must
CML be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL 10 Power, Analog PLL Power, 1.8V ±5%
VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML 14 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD 28 Power, Digital Digital Power, 1.8V ±5%
Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V
DDIO
.
VDDIO 25
V
DDIO
can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%
Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
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