Datasheet

DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Table 2. DS90UB914Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
7:2 RSVD Reserved
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
Oscillator output
0x3C
OSC OUT by OEN/OSSSEL 0x02[5]
divider select
1:0 RW 0
DIVIDER SEL 00: 50M (+/- 30%)
01: 25M (+/- 30%)
1X: 12.5M (+/- 30%)
0x3D-
RESERVED
0x3E
7:5 RSVD Reserved
CML Output 0: CML Loop-through Driver is powered up
0x3F 4 CML OUT Enable RW 1
Enable 1: CML Loop-through Driver is powered down.
3:0 RSVD Reserved
I
2
C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I
2
C
bus. Units are 50 ns for the nominal oscillator
0x40 SCL High Time 7:0 SCL High Time RW 0x82 clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
I
2
C SCL Low Time This field configures the low
pulse width of the SCL output when the De-
Serializer is the Master on the local I
2
C bus.
This value is also used as the SDA setup time
by the I
2
C Slave for providing data prior to
releasing SCL during accesses over the
0x41 SCL Low Time 7:0 SCL Low Time RW 0x82 Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
7:2 RSVD Reserved
1: This bit introduces multiple errors into Back
Force Back
1 RW 0 channel frame.
Channel Error
0x42 CRC Force Error 0: No effect
Force One Back 1: This bit introduces ONLY one error into Back
0 Channel Error RW 0 channel frame. Self clearing bit
0: No effect
0x43-
RESERVED
0x4C
0x4D AEQ Test Mode 7 RSVD Reserved
Select
AEQ Bypass Bypass AEQ and use set manual EQ value
6 RW 0
using register 0x04
5:0 RSVD Reserved
0x4E EQ Value AEQ / Manual Eq Read back the adaptive and manual
7:0 R 0
Readback Equalization value
Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB913Q 10–bit 12–bit 12–bit
Reg 0x14 [2:1] Mode High Frequency Mode Low Frequency Mode
00 50 MHz 37.5 MHz 25 MHz
01 100 MHz 75 MHz 50 MHz
10 50 MHz 37.5 MHz 25 MHz
11 25MHz 18.75 MHz 12.5 MHz
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