Datasheet

DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
Forward Channel
7 R 0 1: If this bit is set, an error may have occurred
Sequence Error
in the control channel operation
0: No forward channel errors have been
detected on the control channel
Clear Sequence Clears the Sequence Error Detect bit
6 RW 0
Error
5 RSVD Reserved
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
4:3 SDA Output Delay RW 0
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
0x22 I
2
C Control 2
to local device registers from across the control
channel. This prevents writes to the
2 Local Write Disable RW 0
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I
2
C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
I
2
C Bus Timer
1 RW 0 50µs
Speedup
0: Watchdog Timer expires after approximately
1s.
Disable I
2
C Bus Watchdog Timer When the I
2
C
Watchdog Timer may be used to detect when
the I
2
C bus is free or hung up following an
invalid termination of a transaction. If SDA is
I
2
C Bus Timer
0 RW 0 high and no signaling occurs for approximately
Disable
1 second, the I
2
C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL
General Purpose Scratch Register
0x23 7:0 GPCR RW 0
Control
7:4 RSVD Reserved
Bist Configured through Pin.
BIST Pin 1: Bist configured through pin.
3 RW 1
Configuration 0: Bist configured through register bit
"reg_24[0]"
0x24 BIST Control
BIST Clock Source
2:1 BIST Clock Source RW 00
See Table 4
BIST Control
0 BIST Enable RW 0 1: Enabled
0: Disabled
Number of Forward channel Parity errors in the
0x25 Parity Error Count 7:0 BIST Error Count R 0
BIST mode.
0x26–0
RESERVED
x3B
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