Datasheet

DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Table 2. DS90UB914Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
7:6 RSVD Reserved
This register can be set only through local I
2
C
access
5 ANAPWDN RW 0 1: Analog power-down : Powers Down the
analog block in the Serializer
0: No effect
4:2 RSVD Reserved
0x01 Reset
Digital Reset Resets the entire digital block
except registers. This bit is self-clearing.
1 Digital Reset 1 RW 0
1: Reset
0: No effect
Digital Reset Resets the entire digital block
including registers. This bit is self-clearing.
0 Digital Reset 0 RW 0
1: Reset
0: No effect
7 RSVD Reserved
6 RSVD Reserved
1: Output PCLK or OSC clock when not
5 Auto-Clock RW 0 LOCKED
0: Only PCLK
1: Selects 8x mode for 10-18 MHz frequency
4 SSCG LFMODE RW 0 range in SSCG
0: SSCG running at 4X mode
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (kHz) PCLK/2168, fdev +/-0.50%
0010: fmod (kHz) PCLK/2168, fdev +/-1.00%
General
0011: fmod (kHz) PCLK/2168, fdev +/-1.50%
0x02
Configuration 0
0100: fmod (kHz) PCLK/2168, fdev +/-2.00%
0101: fmod (kHz) PCLK/1300, fdev +/-0.50%
0110: fmod (kHz) PCLK/1300, fdev +/-1.00%
0111: fmod (kHz) PCLK/1300, fdev +/-1.50%
3:0 SSCG RW 0 1000: fmod (kHz) PCLK/1300, fdev +/-2.00%
1001: fmod (kHz) PCLK/868, fdev +/-0.50%
1010: fmod (kHz) PCLK/868, fdev +/-1.00%
1011: fmod (kHz) PCLK/868, fdev +/-1.50%
1100: fmod (kHz) PCLK/868, fdev +/-2.00%
1101: fmod (kHz) PCLK/650, fdev +/-0.50%
1110: fmod (kHz) PCLK/650, fdev +/-1.00%
1111: fmod (kHz) PCLK/650, fdev +/-1.50%
Note: This regsiter should be changed only
after disabling SSCG.
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