Datasheet

DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Table 1. DS90UB913Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
7:5 RSVD Reserved
SDA Output Delay This field configures output delay on
the SDA output. Setting this value will increase output
delay in units of 50ns. Nominal output delay values for
SCL to SDA are:
4:3 SDA Output Delay RW 00
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to Local Registers Setting this bit
to a 1 will prevent remote writes to local device registers
from across the control channel. This prevents writes to
2 Local Write Disable RW 0
the Serializer registers from an I
2
C master attached to
0x0F I
2
C Master Config the Deserializer. Setting this bit does not affect remote
access to I
2
C slaves at the Serializer.
Speed up I2C Bus Watchdog Timer
I2C Bus Timer 1: Watchdog Timer expires after approximately 50
1 RW 0
Speed up microseconds
0: Watchdog Timer expires after approximately 1 second.
1. Disable I
2
C Bus Watchdog Timer When the I
2
C
Watchdog Timer may be used to detect when the I
2
C bus
is free or hung up following an invalid termination of a
I2C Bus Timer transaction. If SDA is high and no signalling occurs for
0 RW 0
Disable approximately 1 second, the I
2
C bus will assumed to be
free. If SDA is low and no signaling occurs, the device
will attempt to clear the bus by driving 9 clocks on SCL
0: No effect
7 RSVD Reserved
Internal SDA Hold Time. This field configures the amount
6:4 SDA Hold Time RW 0x1 of internal hold time provided for the SDA input relative to
0x10 I2C Control the SCL input. Units are 50ns.
I2C Glitch Filter Depth This field configures the maximum
3:0 I2C Filter Depth RW 0x7 width of glitch pulses on the SCL and SDA inputs that will
be rejected. Units are 10ns.
I2C Master SCL High Time This field configures the high
pulse width of the SCL output when the Serializer is the
Master on the local I2C bus. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
0x11 SCL High Time 7:0 SCL High Time RW 0x82
set to provide a minimum (4µs + 1µs of rise time for
cases where rise time is very fast) SCL high time with the
internal oscillator clock running at 26MHz rather than the
nominal 20MHz.
I
2
C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the Master
on the local I
2
C bus. This value is also used as the SDA
setup time by the I
2
C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
0x12 SCL LOW Time 7:0 SCL Low Time RW 0x82 Control Channel. Units are 50 ns for the nominal
oscillator clock frequency. The default value is set to
provide a minimum (4.7µs + 0.3µs of fall time for cases
where fall time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than the nominal
20MHz.
General Purpose 1: High
0x13 7:0 GPCR[7:0] RW 0
Control 0: Low
26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q