Datasheet

DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
Back-channel CRC Checker Enable
RX CRC Checker
7 RW 1 1:Enabled
Enable
0:Disabled
Forward channel Parity Generator Enable
TX Parity
6 RW 1 1: Enable
Generator Enable
0: Disable
Clear CRC Error Counters.
This bit is NOT self-clearing.
5 CRC Error Reset RW 0
1: Clear Counters
0: Normal Operation
Automatically Acknowledge I2C Remote Write
The mode works when the system is LOCKed.
1: Enable: When enabled, I
2
C writes to the Deserializer
I
2
C Remote Write (or any remote I2C Slave, if I
2
C PASS ALL is enabled)
4 RW 0
Auto Acknowledge are immediately acknowledged without waiting for the
Deserializer to acknowledge the write. The accesses are
then remapped to address specified in 0x06.
0: Disable
1: Enable Forward Control Channel pass-through of all
General
I
2
C accesses to I2C Slave IDs that do not match the
0x03
Configuration
Serializer I2C Slave ID. The I
2
C accesses are then
3 I
2
C Pass All RW 0 remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of
I
2
C accesses to I
2
C Slave IDs matching either the remote
Deserializer Slave ID or the remote Slave ID.
I
2
C Pass-Through Mode
I
2
C
2 RW 1 0: Pass-Through Disabled
PASSTHROUGH
1: Pass-Through Enabled
1:Enabled : When enabled this registers overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
1 OV_CLK2PLL RW 0 selection through register 0x35 in the Serializer
0: Disabled : When disabled,cClock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
0 TRFB RW 1 Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
0x04 RESERVED
7 RSVD RW 0 Reserved
6 RSVD RW 0 Reserved.
Allows overriding mode select bits coming from back-
MODE_OVERRID channel
5 RW 0
E 1: Overrides MODE select bits
0: Does not override MODE select bits
0x05 Mode Select MODE_UP To Indicates that the status of mode select from Deserializer
4 R 0
DATE is up to date
Pin_MODE_12–bit 1: 12 bit high frequency mode is selected.
3 R 0
High Frequency 0: 12 bit high frequency mode is not selected.
Pin_MODE_10–bit 1: 10 bit mode is selected.
2 R 0
mode 0: 10 bit mode is not selected.
1:0 RSVD Reserved
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