Datasheet

FPD-Link III
Bi-Directional
Control Channel
Image
Sensor
ECU Module
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
SDA
SCL
DOUT-
RIN-
DOUT+
RIN+
Camera Unit
10 or 12
DATA
HSYNC
VSYNC
PCLK
Pixel Clock
SDA
SCL
Microcontroller
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
SDA
SCL
PCLK
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
SDA
SCL
Camera Data
DS90UB914Q
Deserializer
DS90UB913Q
Serializer
GPO[3:0]
GPO[3:0]
4
GPIO[3:0]
4
GPIO[3:0]
Camera Data
DIN
10 or
12
DS90UB913Q - SERIALIZER
Clock
Gen
Timing and
Control
DOUT-
DOUT+
Input Latch
FIFO
Decoder
Encoder
Serializer
PLL
I2C Controller
Encoder
R
T
R
T
PCLK
SDA
SCL
GPO[3:0]
4
PDB
ID[x]
HSYNC
VSYNC
RIN0-
DS90UB914Q - DESERIALIZER
RIN0+
Timing and
Control
FIFO
Encoder
I2C
Controller
Decoder
Deserializer
Decoder
Output Latch
Clock
Gen
CDR
R
T
R
T
PDB
BISTEN
OEN
RIN1-
RIN1+
ROUT
HSYNC
VSYNC
GPIO[3:0]
PCLK
LOCK
PASS
IDx[0]
SDA
SCL
2:1
4
10
or
12
SEL
MODE
MODE
IDx[1]
Adaptive Eq.
DSP, FPGA/
µ-Processor/
ECU
Deserializer
DS90UB913Q
Serializer
FPD-Link III
Bidirectional
Control Channel
DS90UB914Q
Bidirectional
Control Bus
Bidirectional
Control Bus
Parallel
Data In
Parallel
Data Out
10 or 12
2
2
Megapixel
Imager/Sensor
10 or 12
GPO
GPIO
4
4
2
HSYNC,
VSYNC
2
HSYNC,
VSYNC
DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Typical Application Diagram
Figure 1. Typical Application Circuit
Block Diagrams
Figure 2. Block Diagram
Figure 3. Application Block Diagram
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