Datasheet

Z
Diff
= 100:
100:
D
OUT
+
D
OUT
-
100 nF
100 nF
SCOPE
BW 8 4.0 GHz
50:
50:
80%
20%
80%
20%
Vdiff = 0V
t
LHT
t
HLT
Vdiff
Vdiff = (D
OUT
+) - (D
OUT
-)
PCLK
(RFB = H)
D
IN
/R
OUT
Signal Pattern
Device Pin Name
T
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
r
t
BUF
DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I
2
C Compliant
(1)
(continued)
Over recommended supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
V
IL
Input Low Level SDA and SCL GND 0.3*V
DDIO
V
V
HY
Input Hysteresis >50 mV
V
OL
Output Low Level SDA, I
OL
=0.5mA 0 0.4 V
I
IN
Input Current SDA or SCL, V
IN
=V
DDOP
OR GND —10 10 µA
t
R
SDA Rise Time-READ 430 ns
SDA, RPU = 10kΩ, Cb ≤ 400pF
(Figure 4)
t
F
SDA Fall Time-READ 20 ns
t
SU;DAT
SeeFigure 4 560 ns
t
HD;DAT
SeeFigure 4 615 ns
t
SP
50 ns
C
IN
SDA or SCL <5 pF
AC Timing Diagrams and Test Circuits
Figure 4. Bi-directional Control Bus Timing
Figure 5. “Worst Case” Test Pattern
Figure 6. Serializer CML Output Load and Transition Times
Figure 7. Serializer CML Output Load and Transition Times
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