Datasheet

DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
DCCJ
Deserializer Cycle- PCLK 10–bit mode
440 1760
to-Cycle Clock Jitter SSCG[3:0] = OFF
(3)(1)
PCLK=100MHz
12–bit low frequency
mode 460 730
ps
PCLK=50MHz
12–bit high frequency
mode 565 985
PCLK=75MHz
fdev Spread Spectrum LVCMOS Output Bus 10 MHz–100 MHz
±0.5 to
Clocking Deviation SSC[3:0] = ON (Figure 23)
(1)
%
±1.5
Frequency
fmod Spread Spectrum 10 MHz–100 MHz
Clocking Modulation 5 to 50 kHz
Frequency
(3) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
AC Timing Specifications (SCL, SDA) - I
2
C Compliant
Over recommended supply and temperature ranges unless otherwise specified.(Figure 4)
Symbol Parameter Conditions Min Typ Max Units
Recommended Input Timing Requirements
Standard Mode >0 100 kHz
f
SCL
SCL Clock Frequency
Fast Mode >0 400 kHz
Standard Mode 4.7 µs
t
LOW
SCL Low Period
Fast Mode 1.3 µs
Standard Mode 4.0 µs
t
HIGH
SCL High Period
Fast Mode 0.6 µs
Standard Mode 4.0 µs
Hold time for a start or a repeated start
t
HD:STA
condition
Fast Mode 0.6 µs
Standard Mode 4.7 µs
Set Up time for a start or a repeated
t
SU:STA
start condition
Fast Mode 0.6 µs
Standard Mode 0 3.45 µs
t
HD:DAT
Data Hold Time
Fast Mode 0 900 ns
Standard Mode 250 ns
t
SU:DAT
Data Set Up Time
Fast Mode 100 ns
Standard Mode 4.0 µs
t
SU:STO
Set Up Time for STOP Condition
Fast Mode 0.6 µs
Standard Mode 4.7 µs
t
BUF
Bus Free time between Stop and Start
Fast Mode 1.3 µs
Standard Mode 1000 ns
t
r
SCL & SDA Rise Time
Fast Mode 300 ns
Standard Mode 300 ns
t
f
SCL & SDA Fall Time
Fast Mode 300 ns
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I
2
C Compliant
(1)
Over recommended supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
Recommended Input Timing Requirements
V
IH
Input High Level SDA and SCL 0.7*V
DDIO
V
DDIO
V
(1) Specification is ensured by design.
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