Datasheet
DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver Output 10–bit mode PCLK (Figure 18) 10 50
Clock Period
12–bit high frequency mode 13.33 66.66 ns
12–bit low frequency mode 10 100
t
PDC
PCLK Duty Cycle 10–bit mode PCLK 45 50 55
12–bit high frequency mode 40 50 60 %
12–bit low frequency mode 40 50 60
LVCMOS Low-to- V
DDIO
: 1.71V to 1.89V or 3.0V PCLK
t
CLH
1.3 2 2.8
High Transition Time to 3.6V,
C
L
= 8 pF (lumped load) ns
t
CHL
LVCMOS High-to-
Default Registers
1.3 2 2.8
Low Transition Time
(Figure 16)
(1)
LVCMOS Low-to- V
DDIO
: 1.71V to 1.89V or 3.0V ROUT[11:0], HS, VS
t
CLH
1 2.5 4
High Transition Time to 3.6V,
C
L
= 8 pF (lumped load) ns
t
CHL
LVCMOS High-to-
Default Registers
1 2.5 4
Low Transition Time
(Figure 16)
(1)
ROUT Setup Data to V
DDIO
: 1.71V to 1.89V or 3.0V ROUT[11:0], HS, VS
t
ROS
0.38T 0.5T
PCLK to 3.6V,
ns
C
L
= 8 pF (lumped load)
t
ROH
ROUT Hold Data to
0.38T 0.5T
Default Registers (Figure 18)
PCLK
10–bit mode 154T 158T
Default Registers 12–bit low frequency
109T 112T
t
DD
Deserializer Delay Register 0x03h b[0] (RRFB = 1) mode ns
(Figure 17)
(1)
12–bit high frequency
73T 75T
mode
With Adaptive Equalization 10–bit mode 15 22
(Figure 15)
12–bit low frequency
Deserializer Data 15 22
t
DDLT
mode ms
Lock Time
12–bit high frequency
15 22
mode
t
RCJ
Receiver Clock Jitter PCLK 10–bit mode
20 30
SSCG[3:0] = OFF
(1)
PCLK=100MHz
12–bit low frequency
mode 22 35
ps
PCLK=50MHz
12–bit high frequency
mode 45 90
PCLK=75MHz
t
DPJ
Deserializer Period PCLK 10–bit mode
170 815
Jitter SSCG[3:0] = OFF
(2)(1)
PCLK=100MHz
12–bit low frequency
mode 180 330
ps
PCLK=50MHz
12–bit high frequency
mode 300 515
PCLK=75MHz
(1) Specification is ensured by characterization and is not tested in production.
(2) t
DPJ
is the maximum amount the period is allowed to deviate measured over 30,000 samples.
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