Datasheet

DS90UB913Q, DS90UB914Q
www.ti.com SNLS420B –JULY 2012–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LHT
CML Low-to-High Transition R
L
= 100Ω (Figure 6)
150 330 ps
Time
t
HLT
CML High-to-Low Transition R
L
= 100Ω (Figure 6)
150 330 ps
Time
t
DIS
Data Input Setup to PCLK Serializer Data Inputs 2 ns
(Figure 12)
t
DIH
Data Input Hold from PCLK 2 ns
t
PLD
Serializer PLL Lock Time R
L
= 100Ω
(1)(2)
, (Figure 13) 1 2 ms
t
SD
Serializer Delay
(2)
R
T
= 100Ω
10–bit mode
32.5T 38T 44T ns
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
R
T
= 100Ω
12–bit mode
11.75T 13T 15T ns
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
t
JIND
Serializer Output Serializer output intrinsic deterministic
Deterministic Jitter jitter . Measured (cycle-cycle) with 0.13 UI
PRBS-7 test pattern
(3)(4)
t
JINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter (cycle-cycle). Alternating-1,0 0.04 UI
pattern.
(3)(4)
t
JINT
Peak-to-peak Serializer Serializer output peak-to-peak jitter
Output Jitter includes deterministic jitter, random
jitter, and jitter transfer from serializer 0.396 UI
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
(3)(4)
λ
STXBW
Serializer Jitter Transfer PCLK = 100MHz
2.2
Function -3 dB Bandwidth
(5)
10–bit mode. Default Registers
PCLK = 75MHz 2.2
12–bit high frequency mode. Default
MHz
Registers
PCLK = 50MHz 2.2
12–bit low frequency mode. Default
Registers
δ
STX
Serializer Jitter Transfer PCLK = 100MHz
1.06
Function (Peaking)
(5)
10–bit mode. Default Registers
PCLK = 75MHz 1.09
12–bit high frequency mode. Default
dB
Registers
PCLK = 50MHz 1.16
12–bit low frequency mode. Default
Registers
δ
STXf
Serializer Jitter Transfer PCLK = 100MHz
400
Function (Peaking 10–bit mode. Default Registers
Frequency)
(5)
PCLK = 75MHz 500
12–bit high frequency mode. Default
kHz
Registers
PCLK = 50MHz 600
12–bit low frequency mode. Default
Registers
(1) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T
A
= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(5) Specification is ensured by characterization and is not tested in production.
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