Datasheet

DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013 www.ti.com
Electrical Characteristics
(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
I
DDR
Deserializer (Rx) VDDn V
DDn
=1.89V f=100MHz,
64 110
Supply Current C
L
=4pF 10–bit mode
(includes load current) Worst Case Pattern
f=75MHz,
12–bit high freq 67 114
mode
f=50MHz,
12–bit low freq 63 96
mode
mA
V
DDn
=1.89V f=100MHz,
57
C
L
=4pF 10–bit mode
Random Pattern
f=75MHz,
12–bit high freq 60
mode
f=50MHz,
12–bit low freq 56
mode
I
DDRZ
Deserializer (Rx) PBB=0V
VDDIO=1.89V
Supply Current Power- All other LVCMOS 42 400
Default Registers
down Inputs=0V
µA
PBB=0V VDDIO=3.6V
All other LVCMOS Default Registers 42 400
Inputs=0V
I
DDIORZ
Deserializer (Rx) VDD PDB = 0V V
DDIO
= 1.89V 8 40
Supply Current Power- All other LVCMOS µA
V
DDIO
= 3.6V
360 800
down Inputs = 0V
Recommended Serializer Timing for PCLK
(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq Min Typ Max Units
t
TCP
Transmit Clock Period 10–bit Mode 10 T 50 ns
12–bit high frequency mode 13.33 T 66.66 ns
12–bit low frequency mode 20 T 100 ns
t
TCIH
Transmit Clock Input High
0.4T 0.5T 0.6T ns
Time
t
TCIL
Transmit Clock Input Low
0.4T 0.5T 0.6T ns
Time
t
CLKT
PCLK Input Transition 20MHz–100 MHz, 10 bit mode 0.5T 2.5T 0.3T ns
Time
15MHz -75MHz, 12 bit high
0.5T 2.5T 0.3T ns
(Figure 11)
frequency mode
10MHz-50MHz, 12 bit low
0.5T 2.5T 0.3T ns
frequency mode
t
JIT0
PCLK Input Jitter (PCLK Refer to f=10–100M
0.1T ns
from imager mode) Jitter freq>f/40 Hz
t
JIT1
PCLK Input Jitter Refer to f=10–100M
1T ns
(External Oscillator mode) Jitter freq>f/40 Hz
t
JIT2
External Oscillator Jitter 0.1 UI
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
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