Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

DS90UB913A-CXEVM & DS90UB914A-CXEVM

REV A User's Guide

User's Guide

Literature Number: SNLU135

JUNE 2013

Summary of content (41 pages)

PAGE 1
DS90UB913A-CXEVM & DS90UB914A-CXEVM REV A User's Guide User's Guide Literature Number: SNLU135 JUNE 2013
PAGE 2
Chapter 1 SNLU135 – JUNE 2013 Introduction 1.1 Overview The Texas Instruments DS90UB913A-CXEVM & DS90UB914A-CXEVM REV A Evaluation Modules (EVM) provides an easy way to evaluate the operation and performance of the DS90UB913AQ / DS90UB914AQ FPD-Link III Serializer/Deserializer. (A) The DS90UB913A-CXEVM REV A contains the DS90UB913AQ Evaluation board. (B) The DS90UB914A-CXEVM REV A contains the DS90UB914AQ Evaluation board Other components required: Power supply (5V) and 50Ω coaxial cable.
PAGE 3
Quick Setup of EVM www.ti.com 1.2 Quick Setup of EVM Figure 1-2.
PAGE 4
Quick Setup of EVM www.ti.com Figure 1-3.
PAGE 5
Operation www.ti.com 1.3 Operation Make sure S1, S2, JP8, JP13 of Serializer board and S1, S2, JP6, JP12 of Deserializer board are configured as shown in Figure 1-2 and Figure 1-3. 1. Connect the DS90UB913AQ and DS90UB914AQ Evaluation boards using a coax cable. 2. Connect the 5V power supply to Deserializer board (recommended current limit is 300mA) and apply power as shown in Figure 2-1. 3. Look for the LED D2 to light up on the DS90UB914AQ board.
PAGE 6
Chapter 2 SNLU135 – JUNE 2013 Board Setup Details This section describes the connectors and jumpers on the board as well as how to properly connect, set up and use the DS90UB913A/914A REV A EVM in detail. 2.1 Power Connections 1. Connect an external 5V to pin 1 or 2 of JP5, on Deserializer board. (Refer Figure 2-1) 2. Connect ground to pin 3 or 4 of JP5, on Deserializer board. (Refer Figure 2-1) 3.
PAGE 7
LVCMOS Input Connector Description (On DS90UB913AQ board) www.ti.com Figure 2-2. Serial link connection using a single 50Ω coaxial cable 2.3 LVCMOS Input Connector Description (On DS90UB913AQ board) JP1 – GPO0, GPO1, CLK OUT, CLK IN, DIN[11:0], HSYNC, VSYNC, PCLK IN are the input pins for the LVCMOS interface on Serializer board. The even numbered pins are the input signals. All the odd numbered pins are connected to VSS. Refer to Figure 2-3 below. JP10 and JP1 pins are not connected. Figure 2-3.
PAGE 8
Factory Set Switch Settings and Jumpers Default Configuration www.ti.com JP1 and JP7 pins are not connected. Figure 2-4. Parallel Output Connector on Deserializer Board 2.5 Factory Set Switch Settings and Jumpers Default Configuration 2.5.1 Serializer Board default configuration S1, S2, JP8 and JP13 of Serializer board are factory configured as shown in Figure 1-2 for plug and play operation. 1. The S1 switch is factory set as shown in Figure 2-5. The PDN switch (S1.
PAGE 9
Factory Set Switch Settings and Jumpers Default Configuration www.ti.com Only one switch is allowed to be in SELECT mode at a time. Figure 2-6. Switch S2: Default settings on Serializer Board 3. S3 is a momentary switch, which is present on the top right corner of the SER board. Press this switch to clear the output of one shot latches for low pulse on GPO0 and GPO1. 4. S4 is a momentary switch for Transmitter Power Down. 5. On JP8 and JP13, a 2-pin jumper is factory placed as shown in Figure 1-2.
PAGE 10
Factory Set Switch Settings and Jumpers Default Configuration www.ti.com Figure 2-7. Switch S1: Default settings on Deserializer Board Table 2-1. Switch S1: Deserializer Board Switch reference Function S1.1-PDN High High: Deserializer is enabled and is ON. Low: Deserializer is in Sleep (power down mode). In this mode, programmed control register data are NOT retained and reset to default values. S1.
PAGE 11
Factory Set Switch Settings and Jumpers Default Configuration www.ti.com 2. The S2 switch is factory set as shown below in Figure 2-8. This will configures the SER/DES link in 10 bit mode. Only one switch is allowed to be in SELECT mode at a time. Figure 2-8. Switch S2: Default settings on Deserializer Board Table 2-2. Switch S2: Deserializer Board Switch reference Default Setting Frequency Range supported Function S2.
PAGE 12
Chapter 3 SNLU135 – JUNE 2013 Using I2C 3.1 Default Addresses The default 7-bit I2C address of DS90UB913AQ is set to 0x58 (101 1000) using suitable resistor divider on ID[x] pin. Also, 7-bit I2C address of DS90UB914AQ is set to 0x60 (110 0000) using suitable resistor dividers on pins IDx[0] and IDx[1]. Change resistor R25 on Serializer board and R32, R33 on Deserializer board to change the address of these devices, refer device datasheet for more information. 3.
PAGE 13
SPA Dongle Board www.ti.com (3) (4) Figure 3-2. Devices Tab 2. To communicate with a particular device, go to Tools > EEPROM Setup. Figure 3-3.
PAGE 14
SPA Dongle Board (5) (6) www.ti.com 3. Select the current device, which will be highlighted in BLUE as shown in Figure 3-4. Figure 3-4. ALP EEPROM Setup Window1 4. Select a device profile, which is DS90UB913 for example and then click on Write EEPROM.
PAGE 15
SPA Dongle Board www.ti.com (7) (8) Figure 3-5. Selecting Device Profile 5. EEPROM Status will prompt as shown inFigure 3-6, press OK. Figure 3-6. EEPROM Status 6. ALP EEPROM Setup window will show up with device name DS90UB913 as highlighted in Figure 3-7. Press OK.
PAGE 16
SPA Dongle Board (9) (10) www.ti.com Figure 3-7. ALP EEPROM Setup Window2 7. Under the Devices tab click on DS90UB913 to select the device and open up the device profile and its associated tabs.
PAGE 17
SPA Dongle Board www.ti.com (11) (12) Figure 3-8.
PAGE 18
Chapter 4 SNLU135 – JUNE 2013 Additional Features 4.1 Eye Monitor – CMLOUTP/N Figure 4-1. Top view of CML access points on Deserializer Board Connector J3 connects CMLOUTP (or TEST+) and J4 connects to CMLOUTN (or TEST-), which are present on left hand side of DS90UB914A-CXEVM board. CMLOUTP/N must be enabled by register, 0x3F[4] = 0, to be able to monitor the FPD-Link III serial stream. 4.2 Differential operation over a pair of Coax cables For differential operation, 1.
PAGE 19
Optional use of header provided for external Imager and Host www.ti.com On DES board, • Mount L5 (2.7uH), L6 (2.7uH) • Put jumpers on JP3 and JP4 to match the polarity of supply (check on pin2 of each header) Figure 4-2. Power over STP: SER configuration Figure 4-3. Power over STP: DES configuration 4.
PAGE 20
Optional use of header provided for external Imager and Host www.ti.com R82, R83, R84. It is recommended to remove JP1. 2. On Deserializer board, populate JP7, R70, R71, R72, R73, R75, R76, R77, R78, R79, R80, R81, R82, R84, R85, R86. It is recommended to remove JP1.
PAGE 22
DS90UB913A-CXEVM Serializer Board Schematic A.1 www.ti.com DS90UB913A-CXEVM Serializer Board Schematic 1. DS90UB913AQ Serializer Place L1, R28 about 2" from U1 1UF AT BOTTOM, AT VDD PIN TO DAP 0.1UF AT TOP, CLOSE TO VDD PIN VDD1P8 U2 DOUTP_HSD_Z100 DOUTN_HSD_Z100 L1 C1 0.1UF C2 1UF C3 0.1UF C9 1UF 5 VCC NC GND IO1 4 1K@100MHz C10 0.1UF C11 1UF GND VDD5V 1 2 3 IO2 C25 10UF ESD-NO-STUFF GND VDD3P3 GND GND GND ESD placed closed to P1 C5 1UF C6 0.
PAGE 23
DS90UB913A-CXEVM Serializer Board Schematic www.ti.com 2. Power to Serializer board External 5V IN U3 LP38693MP-ADJ VDD5V 3.3V ADJ LDO JP4 4 1 2 3 4 VIN VOUT R48 10K ADJ C32 0.1UF VEN R49 0 - NO-STUFF U3_Pin3 16.5K R57 10K C37 C38 0.1UF 10UF 5 C33 4.7UF 1 U3_Pin3 R56 2 GND C28 22UF 4 HEADER 3 GND VDD1P8 SELECT 1.8V ADJ LDO OR 1.8V FIXED TO U1 U4 LP38693MP-ADJ 1.8V ADJ LDO JP8 VIN VOUT R50 10K ADJ C34 0.1UF R51 0 - NO-STUFF VDD3P3 HEADER 3 4.53K R59 10K C39 C40 0.
PAGE 24
DS90UB913A-CXEVM Serializer Board Schematic www.ti.com 3.
PAGE 25
DS90UB913A-CXEVM Serializer Board Schematic www.ti.com 4. Buck Regulator on Serializer board VIN_LDO 3 TPS65320 20V TO 5V BUCK REGULATOR BOOT 1 C54 0.1UF C0402 L12 VDD20V C52 4.7uF_50V C1206 C56 22uF C1206 C57 22uF C1206 C66 0.1uF_50V C0603 VDD20V GND GND GND GND VIN R93 0_DNL R0603 R91 10K R0603 TPS65320-Q GND 8 7 R92 10K R0603 Rsn Csn EN1 EN2 FB1 9 LDO_OUT 10 15 GND VDD3P3 GND C63 10UF C0805 C64 0.1UF_DNL C0402 C65 0.
PAGE 26
DS90UB914A-CXEVM Deserializer Board Schematic A.2 www.ti.com DS90UB914A-CXEVM Deserializer Board Schematic 1. DS90UB914AQ Deserializer Power & bypass DS90UB914-PAGE2.SCH PULL-UP PLACED NEAR HEADER 5 R1 R2 R3 R4 R5 R6 R7 R8 R9 R13 R14 R15 R16 R17 R18 R19 R20 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K GND_A 1 2 3 IO2 VCC NC GND IO1 4 GND_A VDD5V_A U2 RIN0P_HSD_ZDIFF RIN0N_HSD_ZDIFF R48 49.
PAGE 27
DS90UB914A-CXEVM Deserializer Board Schematic www.ti.com 2. Power to Deserializer board PLACE 0.1UF TOP SIDE NEAR TO VDD PIN OF U1 PLACE 1UF OR 22UF ON BOTTOM SIDE 3.3V ADJ LDO U3 JP5 VDD5V_A 4 1 2 3 4 VIN VOUT R54 10K C21 0.1UF 1 C22 4.7UF R55 0 -NO-STUFF VDD1P8_A 16.5K C62 10UF VIN VOUT GND_A C40 0.1UF C41 1UF C50 0.1UF ADJ VEN R57 0-NO-STUFF R61 2 C42 0.1UF 1 2 3 C53 0.1UF C18 10UF For VDDD C29 C30 0.1UF 10UF C56 0.1UF SELECT 1.8V ADJ LDO OR 1.8V FIXED L8 L7 2.
PAGE 28
DS90UB914A-CXEVM Deserializer Board Schematic www.ti.com 3.
PAGE 29
DS90UB914A-CXEVM Deserializer Board Schematic www.ti.com 4. Buck Regulator on Deserializer board VIN_LDO 3 TPS65320 20V TO 5V BUCK REGULATOR BOOT 1 C73 0.1UF C0402 VDD5V_A L12 VDD20V_A MBRS1540T3 RAPC722 C63 4.7uF_50V C1206 C64 22uF C1206 C65 22uF C1206 C77 0.
PAGE 30
www.ti.
PAGE 31
Appendix B SNLU135 – JUNE 2013 Bill of Materials B.1 DS90UB913A-CXEVM Serializer Board BOM Table B-1. DS90UB913A-CXEVM BOM Qty. Reference Part PCB footprint MFR and Part# 18 R21, R47, R67, R68, R69, R70,R72, R73, R75, R76, R77, R78, R79, R81, R82, R83, R84 , R106, R107 0-NO-STUFF 0402 Panasonic ERJ-2GE0R00X, 0.1W 6 R10, R25, R35, R40, R54, R55, R104, R105 0 0402 Panasonic ERJ-2GE0R00X, 0.0 ohm, 0.1W 2 R42, R44 49.9 0402 Panasonic ERJ-2RKF49R9X, 1%, 100ppm, 0.
PAGE 32
DS90UB913A-CXEVM Serializer Board BOM www.ti.com Table B-1. DS90UB913A-CXEVM BOM (continued) Qty. 32 Reference Part PCB footprint MFR and Part# 1 C58 3.9NF 0402 KEMET,C0402C392K4RACTU,CAP CER 3900PF 16V 10% X7R 1 C53 78.13NF 0402 KEMET,C0402C823K4RACTU,CAP CER 0.082UF 16V 10% X7R 24 C1, C3, C4, C6, C7, C10, C13, C23, C30, C32, C34, C36, C37, C39, C47, C48, C49, C50, C51, C54, C101, C102 0.1UF 0402 Murata GRM155R71C104KA88D, 0.1uF, 16V, 10%, X7R 3 C62, C64, C65 0.
PAGE 33
DS90UB914A-CXEVM Deserializer Board BOM www.ti.com Table B-1. DS90UB913A-CXEVM BOM (continued) Qty. B.2 Reference Part PCB footprint MFR and Part# 1 JP1 HEADER 19X2 TE Connectivity, 0.1 pitch, 2x30 pin header, CUT to FIT, 3-87215-0 6 JP2, JP3, JP6, JP7, JP8, JP9, JP13 HEADER 3 Amp/Tyco, 0.1" pitch 1 JP4 HEADER 4 Molex, 1x4 header pin, 0.1 pitch 1 JP5 HDR_2 1X2 HEADER 1 JP10 HEADER 16X2 Use 2x30 female header, 0.
PAGE 34
DS90UB914A-CXEVM Deserializer Board BOM www.ti.com Table B-2. DS90UB914A-CXEVM BOM (continued) 34 Qty. Reference Part PCB footprint MFR and Part# 2 R55, R57, R58, R97, R99 0-NO-STUFF 0603 Panasonic ERJ-3GEY0R00V, 0ohm, 0603 2 R83, R87 1K 0603 Panasonic ERJ-3EKF1001V, 1Kohm, 1%, 0603 1 R61 4.53K 0603 Panasonic ERJ-3EKF4531V, 1%, 100ppm, 0.1W 1 R106 5.69K 0603 Panasonic,PAT0603E5691BST1, 0.15W 0.1% 7 R51, R54, R56, R60, R62, R96, R98 10K 0603 Panasonic ERJ-3EKF1002V, 1%, 0.
PAGE 35
DS90UB914A-CXEVM Deserializer Board BOM www.ti.com Table B-2. DS90UB914A-CXEVM BOM (continued) Qty. Reference Part 1 L1 KA4909-NOSTUFF PCB footprint MFR and Part# Coilcraft differential choke KA4909-AL 1 L2 100UH CoilCraft, MSS7314T-104ML, 100UH+-20% 2 L3, L8 1K@100MHz 0603 Murata, Ferrite Bead, 1K @100MHz, BLM18AG102SN1D 1 L4 NO-STUFF Murata_DLW21 Murata common mode choke, DLW21SN261XQ2 3 L5, L6 10UH-NOSTUFF 1 L7 2.2UH 1 L9 5.6UH CoilCraft, 1008PS-562KL, 5.
PAGE 36
DS90UB914A-CXEVM Deserializer Board BOM www.ti.com Table B-2. DS90UB914A-CXEVM BOM (continued) 36 Qty.
PAGE 37
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
PAGE 38
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
PAGE 39
【Important Notice for Users of this Product in Japan】】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
PAGE 40
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
PAGE 41
IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that incorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remains responsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.