Datasheet

DS90UB903Q, DS90UB904Q
www.ti.com SNLS332E –JUNE 2010–REVISED APRIL 2013
Electrical Characteristics
(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Differential Threshold
V
TH
+90
High Voltage
(Figure 10) mV
V
TL
Differential Threshold
-90
Low Voltage
V
IN
Differential Input
RIN+ - RIN- 180 mV
Voltage Range
I
IN
Input Current V
IN
= V
DD
or 0V, V
DD
= 1.89V -20 ±1 +20 µA
R
T
Differential Internal
Termination Differential across RIN+ and RIN- 80 100 120 Ω
Resistance
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
I
DDT
R
T
= 100Ω
Serializer (Tx)
WORST CASE pattern 62 90
VDDn = 1.89V
VDDn Supply Current
(Figure 5)
PCLK = 43 MHz mA
(includes load
Default Registers
R
T
= 100Ω
current)
55
RANDOM PRBS-7 pattern
I
DDIOT
VDDIO = 1.89V
PCLK = 43 MHz 2 5
Serializer (Tx)
R
T
= 100Ω
Default Registers
VDDIO Supply
WORST CASE pattern mA
Current (includes load
VDDIO = 3.6V
(Figure 5)
current)
PCLK = 43 MHz 7 15
Default Registers
I
DDTZ
V
DDn
= 1.89V 370 775
Serializer (Tx) Supply PDB = 0V; All other
I
DDIOTZ
V
DDIO
= 1.89V 55 125 µA
Current Power-down LVCMOS Inputs = 0V
V
DDIO
= 3.6V 65 135
I
DDR
V
DDn
= 1.89V, C
L
= 8 pF PCLK = 43 MHz
Deserializer (Rx)
WORST CASE Pattern SSCG[3:0] = ON 60 96
VDDn Supply Current
(Figure 5) Default Registers
(includes load
V
DDn
= 1.89V, C
L
= 8 pF PCLK = 43 MHz
current)
53
RANDOM PRBS-7 Pattern Default Registers
mA
I
DDIOR
V
DDIO
= 1.89V, C
L
= 8 pF
PCLK = 43 MHz
Deserializer (Rx)
WORST CASE Pattern 21 32
Default Registers
VDDIO Supply
(Figure 5)
Current (includes load
V
DDIO
= 3.6V, C
L
= 8 pF PCLK = 43 MHz
current)
49 83
WORST CASE Pattern Default Registers
I
DDRZ
V
DDn
= 1.89V 42 400
Deserializer (Rx)
PDB = 0V; All other
I
DDIORZ
Supply Current V
DDIO
= 1.89V 8 40 µA
LVCMOS Inputs = 0V
Power-down
V
DDIO
= 3.6V 350 800
Recommended Serializer Timing for PCLK
(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock Period 23.3 T 100 ns
t
TCIH
Transmit Clock Input High
0.4T 0.5T 0.6T ns
Time
10 MHz – 43 MHz
t
TCIL
Transmit Clock Input Low
0.4T 0.5T 0.6T ns
Time
t
CLKT
PCLK Input Transition Time
0.5 3 ns
(Figure 11)
f
OSC
Internal oscillator clock
25 MHz
source
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
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