Datasheet

ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
PDB
DAP (GND)
RIN+
RIN-
VDDR
VDDIO3
VDDIO1
VDDIO2
LVCMOS
Parallel
Bus
VDDIO
DS90UB904Q (DES)
C9
C10
C1
C2
C3
VDDD
MODE
RES_PIN46
C4
1.8V
Serial
FPD-Link III
Interface
PCLK
LOCK
PASS
C8
C15 C6
C16 C7
VDDPLL
VDDCML
VDDSSCG
RES_PIN38
RES_PIN39
TP_A
TP_B
LVCMOS
Control
Interface
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
C5
C13
C11
C12
C14
FB1
FB6
FB2
FB3
FB4
FB5
SCL
VDDIO
C18
RPU
C17
RPU
SDA
I2C
Bus
Interface
FB7
FB8
GPI[1]
GPI[0]
GPI
Control
Interface
ID[X]
1.8V
RID
10 k:
Optional
Optional
ROUT18
ROUT19
ROUT20
GPI[3]
GPI[2]
DS90UB903Q, DS90UB904Q
SNLS332E –JUNE 2010–REVISED APRIL 2013 www.ti.com
Figure 38 shows a typical connection of the DS90UB904Q Deserializer.
Figure 38. DS90UB904Q Typical Connection Diagram — Pin Control
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
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