Datasheet
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
PCLK
PDB
DOUT+
DOUT-
VDDCML
DAP (GND)
VDDPLL
VDDT
1.8V
DS90UB903Q (SER)
C4
C10 C5
C6
C1
C2
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
LVCMOS
Parallel
Bus
Serial
FPD-Link III
Interface
MODE
ID[X]
VDDIO
RES
C3
LVCMOS
Control
Interface
VDDIO
1.8V
RID
10 k:
C9
C8
C12
C13
FB1
FB2
FB3
FB4
VDDD
C7
FB5
SCL
VDDIO
C15
RPU
C14
RPU
SDA
I2C
Bus
Interface
FB6
FB7
GPO[1]
GPO[0]
GPO
Control
Interface
C11
Optional
Optional
DIN18
DIN19
DIN20
GPO[3]
GPO[2]
D
OUT
-
D
OUT
+
D
R
IN
-
R
IN
+
R
DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E –JUNE 2010–REVISED APRIL 2013
APPLICATIONS INFORMATION
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 36.
Figure 36. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 37 shows a typical connection of the DS90UB903Q Serializer.
Figure 37. DS90UB903Q Typical Connection Diagram — Pin Control
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