Datasheet

HOST
SER
or
DES
SCL
SDA
RPU RPU
10k
R
ID
SCL
SDA
To other
Devices
ID[x]
1.8V
V
DDIO
DS90UB903Q, DS90UB904Q
SNLS332E –JUNE 2010–REVISED APRIL 2013 www.ti.com
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I
2
C bus through the bidirectional control
channel, slave clock stretching must be supported by the I
2
C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I
2
C slave pulls the SCL line low
prior to the 9th clock of every I
2
C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded.
Any remote access involves the clock stretching period following the transmitted byte, prior to completion of the
acknowledge bit. Since each byte transferred to the I
2
C slave must be acknowledged separately, the clock
stretching will be done for each byte sent by the host controller. For remote accesses, the “Response Delay”
shown is on the order of 12 µs (typical). See Application Note AN-2173 (SNLA131) for more details.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I
2
C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
Figure 29. Bidirectional Control Bus Connection
Table 3. ID[x] Resistor Value – DS90UB903Q
ID[x] Resistor Value - DS90UB903Q Ser
Resistor RID Ω (±0.1%) Address 7'b
(1)
Address 8'b 0 appended (WRITE)
0, GND 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0)
2.0k 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2)
4.7k 7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4)
8.2k 7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6)
12.1k 7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8)
39.0k 7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC)
(1) Specification is ensured by design.
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