Datasheet

I2C
CLK1
CLK
0
Bit 0 to Bit 20
DS90UB904Q
Deserializer
Graphics
Controller
---
Video
Processor
DS90UB903Q
Serializer
I
2
C
PC
I
2
C
Timing
Controller
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PC
SDA
SCL
SDA
SCL
LCD Display
--
Touch Panel
FPD-Link III
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
DS90UB903Q, DS90UB904Q
www.ti.com SNLS332E –JUNE 2010–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS90UB903Q/904Q FPD-Link III chipset is intended for video display applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB903Q transforms a
21-bit wide parallel LVCMOS data bus along with a bidirectional control bus into a single high-speed differential
pair. The high-speed serial bit stream contains an embedded clock and DC-balance information which enhances
signal quality to support AC coupling. The DS90UB904Q receives the single serial data stream and converts it
back into a 21-bit wide parallel data bus together with the bidirectional control channel data bus.
The control channel function of the DS90UB903Q/904Q provides bidirectional communication between the host
processor and display. The integrated control channel transfers data simultaneously over the same differential
pair used for video data interface. This interface offers advantages over other chipsets by eliminating the need
for additional wires for programming and control. The control supports I
2
C port. The bidirectional control channel
offers asymmetrical communication and is not dependent on video blanking intervals.
DISPLAY APPLICATION
The DS90UB903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link.
The DS90UB903Q Serializer accepts a 21-bit parallel data bus along with a bidirectional control bus. The parallel
data and bidirectional control channel information is converted into a single differential link. The integrated
bidirectional control channel bus supports I2C compatible operation for controlling auxiliary data transport to and
from host processor and display module. The DS90UB904Q Deserializer extracts the clock/control information
from the incoming data stream and reconstructs the 21-bit data with control channel data.
Figure 23. Typical Display System Diagram
SERIAL FRAME FORMAT
The DS90UB903Q/904Q chipset will transmit and receive a pixel of data in the following format:
Figure 24. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
The bidirectional control channel data is transferred along with the high-speed forward data over the same serial
link. This architecture provides a full duplex low speed forward channel across the serial link together with a high
speed forward channel without the dependence of the video blanking phase.
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