Datasheet

DS90UB903Q, DS90UB904Q
SNLS332E –JUNE 2010–REVISED APRIL 2013 www.ti.com
Table 2. DS90UB904Q Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
RESERVED 7:6 RESERVED 00'b Reserved
1: Output PCLK or Internal 25 MHz Oscillator clock
Auto Clock 5 AUTO_CLOCK RW 0
0: Only PCLK when valid PCLK present
Output Sleep State Select
OSS Select 4 OSS_SEL RW 0 0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
2
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
SSCG 3:0 SSCG 0000'b 0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
RESERVED 7:6 RESERVED 11'b Reserved
Auto voltage control
VDDIO Control 5 VDDIO CONTROL RW 1 0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
VDDIO Mode 4 VDDIO MODE RW 0
0: 1.8V
1: 3.3V
I
2
C Pass-Through Mode
I
2
C PASS-
3 I
2
C Pass-Through 3 RW 1 0: Disabled
THROUGH
1: Enabled
0: Disable
Auto ACK 2 AUTO ACK RW 0
1: Enable
RESERVED 1 RESERVED 0 Reserved
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB 0 RRFB RW 1 Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
4 EQ Control 7:0 EQ RW 0x00'h 07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
5 RESERVED 7:0 RESERVED 0x00'h Reserved
20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB903Q DS90UB904Q