Datasheet

80%
20%
80%
20%
t
CLKT
t
CLKT
PCLK
V
DD
0V
RIN+
RIN-
V
CM
GND
RIN+
RIN-
V
TH
V
TL
V
ID
V
IN
V
IN
V
ID
D
OUT
+
0V
0V
V
OD+
V
OD+
V
OD-
V
OD-
V
OD
Single Ended
Differential
V
OS
D
OUT
-
(D
OUT
+)-(D
OUT-
)
|
PARALLEL-TO-SERIAL
D
OUT
+
D
OUT
-
21
D
IN
R
L
PCLK
Z
Diff
= 100:
100:
D
OUT
+
D
OUT
-
100 nF
100 nF
SCOPE
BW 8 4.0 GHz
50:
50:
DS90UB903Q, DS90UB904Q
SNLS332E –JUNE 2010–REVISED APRIL 2013 www.ti.com
Figure 7. Serializer CML Output Load and Transition Times
Figure 8. Serializer VOD DC Diagram
Figure 9. Serializer VOD DC Diagram
Figure 10. Differential VTH/VTL Definition Diagram
Figure 11. Serializer Input Clock Transition Times
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