Datasheet

80%
20%
80%
20%
Vdiff = 0V
t
LHT
t
HLT
Vdiff
Vdiff = (D
OUT
+) - (D
OUT
-)
PCLK
(RFB = H)
D
IN
/R
OUT
Signal PatternDevice Pin Name
T
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
r
t
BUF
DS90UB903Q, DS90UB904Q
www.ti.com SNLS332E –JUNE 2010–REVISED APRIL 2013
Figure 4. Bidirectional Control Bus Timing
Bidirectional Control Bus DC Characteristics (SCL, SDA) - I
2
C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
V
IH
0.7 x
Input High Level SDA and SCL V
DDIO
V
V
DDIO
V
IL
0.3 x
Input Low Level Voltage SDA and SCL GND V
V
DDIO
V
HY
Input Hysteresis SDA and SCL >50 mV
I
OZ
TRI-STATE Output Current PDB = 0V, V
OUT
= 0V or V
DD
-20 ±1 +20 µA
I
IN
Input Current SDA or SCL, Vin = V
DDIO
or GND -20 ±1 +20 µA
C
IN
Input Pin Capacitance <5 pF
V
OL
SCL and SDA, V
DDIO
= 3.0V
0.36 V
I
OL
= 1.5 mA
Low Level Output Voltage
SCL and SDA, V
DDIO
= 1.71V
0.36 V
I
OL
= 1 mA
AC Timing Diagrams and Test Circuits
Figure 5. “Worst Case” Test Pattern
Figure 6. Serializer CML Output Load and Transition Times
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