Datasheet

DS90UB903Q, DS90UB904Q
www.ti.com SNLS332E –JUNE 2010–REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
Default Registers
4.571T 4.571T 4.571T
t
DD
Deserializer Delay Register 0x03h b[0] 10 MHz–43 MHz ns
+ 8 + 12 + 16
(RRFB = 1) (Figure 17)
t
DDLT
Deserializer Data Lock Time (Figure 15)
(2)
10 MHz–43 MHz 10 ms
t
RJIT
(Figure 19,
Receiver Input Jitter Tolerance 43 MHz 0.53 UI
Figure 21)
(3)(4)
t
RCJ
10 MHz 300 550
PCLK
Receiver Clock Jitter ps
SSCG[3:0] = OFF
(1)(5)
43 MHz 120 250
t
DPJ
10 MHz 425 600
PCLK
Deserializer Period Jitter ps
SSCG[3:0] = OFF
(1)(6)
43 MHz 320 480
t
DCCJ
10 MHz 320 500
Deserializer Cycle-to-Cycle Clock PCLK
ps
Jitter SSCG[3:0] = OFF
(1)(7)
43 MHz 300 500
fdev Spread Spectrum Clocking ±0.5% to
20 MHz–43 MHz %
LVCMOS Output Bus
Deviation Frequency ±2.0%
SSC[3:0] = ON
fmod Spread Spectrum Clocking 9 kHz to
(Figure 22)
20 MHz–43 MHz kHz
Modulation Frequency 66 kHz
(2) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) t
RJIT
max (0.61UI) is limited by instrumentation and actual t
RJIT
of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) t
DCJ
is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) t
DPJ
is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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