Datasheet

FPGA or ASIC
LVDS I/O
Cable or Backplane
FPGA or ASIC
LVDS I/O
DS90LV804
DS90LV804
SNLS195L –SEPTEMBER 2005–REVISED APRIL 2013 www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ
(1)
Max Units
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
LHT
Differential Low to High Transition
210 300 ps
Time
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of V
OD
(4)
t
HLT
Differential High to Low Transition
210 300 ps
Time
t
PLHD
Differential Low to High
2.0 3.2 ns
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% V
OD
between input to output.
t
PHLD
Differential High to Low
2.0 3.2 ns
Propagation Delay
t
SKD1
Pulse Skew |t
PLHD
–t
PHLD
|
(4)
25 80 ps
t
SKCC
Difference in propagation delay (t
PLHD
or t
PHLD
)
Output Channel to Channel Skew 50 125 ps
among all output channels
(4)
t
SKP
Part to Part Skew Common edge, parts at same temp and V
CC
(4)
1.1 ns
t
JIT
RJ - Alternating 1 and 0 at 400 MHz
(6)
1.1 1.5 psrms
Jitter
(5)
DJ - K28.5 Pattern, 800 Mbps
(7)
15 35 psp-p
TJ - PRBS 2
23
-1 Pattern, 800 Mbps
(8)
30 55 psp-p
t
ON
Time from EN to OUT± change from TRI-STATE to
LVDS Output Enable Time 300 ns
active.
t
OFF
Time from EN to OUT± change from active to TRI-
LVDS Output Disable Time 12 ns
STATE.
(4) Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
ID
= 500mV, 50%
duty cycle at 400 MHz, t
r
= t
f
= 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V
ID
= 500mV, K28.5
pattern at 800 Mbps, t
r
= t
f
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = V
ID
= 500mV, 2
23
-1 PRBS pattern at 800 Mbps, t
r
= t
f
= 50ps (20% to 80%).
Typical Application
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