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DS90LV032A

www.ti.com

SNLS011C –JULY 1999–REVISED APRIL 2013

DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver

Check for Samples: DS90LV032A

FEATURES

DESCRIPTION

The DS90LV032A is a quad CMOS differential line

• >400 Mbps (200 MHz) switching rates

receiver designed for applications requiring ultra low

• 0.1 ns channel-to-channel skew (typical)

power dissipation and high data rates. The device is

• 0.1 ns differential skew (typical)

designed to support data rates in excess of 400 Mbps

(200 MHz) utilizing Low Voltage Differential Signaling

• 3.3 ns maximum propagation delay

(LVDS) technology.

• 3.3V power supply design

The DS90LV032A accepts low voltage (350 mV

• Power down high impedance on LVDS inputs

typical) differential input signals and translates them

• Low Power design (40mW @ 3.3V static)

to 3V CMOS output levels. The receiver supports a

• Interoperable with existing 5V LVDS networks

TRI-STATE

function that may be used to multiplex

outputs. The receiver also supports open, shorted

• Accepts small swing (350 mV typical) VID

and terminated (100Ω) input Fail-safe. The receiver

• Supports open, short and terminated input fail-

output will be HIGH for all fail-safe conditions.

safe

The DS90LV032A and companion LVDS line driver

• Compatible with ANSI/TIA/EIA-644

(eg. DS90LV031A) provide a new alternative to high

• Industrial temp. operating range (-40°C to

power PECL/ECL devices for high speed point-to-

+85°C)

point interface applications.

• Available in SOIC and TSSOP Packaging

Connection Diagram

Order Number DS90LV032ATM

or DS90LV032ATMTC

D-16 and PW-16 Packages

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90LV032A FEATURES DESCRIPTION • • • • • • • • • • The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
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DS90LV032A SNLS011C – JULY 1999 – REVISED APRIL 2013 www.ti.com Functional Diagram Truth Table ENABLES EN EN* L H All other combinations of ENABLE inputs INPUTS OUTPUT RIN+ − RIN− ROUT X Z VID ≥ 0.1V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) −0.3V to +3.9V Input Voltage (RIN+, RIN−) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) −0.3V to (VCC + 0.3V) Maximum Package Power Dissipation @ +25°C D Package 1025 mW PW Package 866 mW Derate D Package 8.2 mW/°C above +25°C Derate PW Package 6.
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DS90LV032A SNLS011C – JULY 1999 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions VCM = +1.2V (2) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCMR Common-Mode Voltage Range VID = 200 mV peak to peak IIN Input Current VIN = +2.
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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter (1) (2) (3) (4) Conditions Min Typ Max Units tPHLD Differential Propagation Delay High to Low CL = 10 pF 1.8 3.3 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.8 3.
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DS90LV032A SNLS011C – JULY 1999 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) CL includes load and test jig capacitance. S1 = VCC for tPZL, and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. Figure 3. Receiver TRI-STATE Delay Test Circuit Figure 4. Receiver TRI-STATE Delay Waveforms TYPICAL APPLICATION Balanced System Figure 5.
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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the application notes found at: http://www.ti.com/ww/en/analog/interface/lvds.shtml. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the drivers .
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DS90LV032A SNLS011C – JULY 1999 – REVISED APRIL 2013 www.ti.com Termination Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best.
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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin No. Name Description 2, 6, RIN+ Non-inverting receiver input pin RIN− Inverting receiver input pin ROUT Receiver output pin 10, 14 1, 7, 9, 15 3, 5, 11, 13 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +3.3V ± 0.
PAGE 10
DS90LV032A SNLS011C – JULY 1999 – REVISED APRIL 2013 www.ti.com Typical Characteristics Figure 6. ICC vs Frequency, four channels switching Figure 7. Typical Common-Mode Range variation with respect to amplitude of differential input Figure 8. Typical Pulse Skew variation versus commonmode voltage Figure 9. Variation in High to Low Propagation Delay versus VCM Figure 10.
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DS90LV032A www.ti.com SNLS011C – JULY 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90LV032ATMTCX Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV032ATMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV032ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0 TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV032ATMX SOIC D 16 2500 367.0 367.0 35.0 DS90LV032ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.
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