Datasheet

Test Circuits and Timing Waveforms (Continued)
Typical Application Diagram
Applications Information
The DS90LV019 has two control pins, which allows the de-
vice to operate as a driver, a receiver or both driver and a re-
ceiver at the same time. There are a few common practices
which should be implied when designing PCB for LVDS sig-
naling. Recommended practices are:
•
Use at least 4 PCB board layer (LVDS signals, ground,
power and TTL signals).
•
Keep drivers and receivers as close to the (LVDS port
side) connector as possible.
•
Bypass each LVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-
layer ceramic (MLC) surface mount capacitors 0.1 µF,
and 0.01 µF in parallel should be used between each V
CC
and ground. The capacitors should be as close as pos-
sible to the V
CC
pin.
•
Use controlled impedance traces which match the differ-
ential impedance of your transmission medium (i.e.,
Cable) and termination resistor.
•
Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
•
Isolate TTL signals from LVDS signals.
MEDIA (CABLE AND CONNECTOR) SELECTION:
•
Use controlled impedance media. The cables and con-
nectors should have a matched differential impedance of
about 100Ω.
DS100053-11
FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
DS100053-13
FIGURE 10. Terminated Input Fail-Safe Circuit
DS100053-12
DS90LV019
www.national.com7