Datasheet

DS90LV004
www.ti.com SNLS190P –APRIL 2005–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol Parameter Conditions Min Max Units
(1)
V
CMR
Common Mode Voltage Range V
ID
= 150 mV, V
DD
= 3.45V 0.05 3.40 V
C
IN2
Input Capacitance IN+ or IN− to V
SS
3.5 pF
I
IN
Input Current V
IN
= 3.45V, V
DD
= V
DDMAX
−10 +10 µA
V
IN
= 0V, V
DD
= V
DDMAX
−10 +10 µA
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V
OD
Differential Output Voltage, R
L
= 100Ω external resistor between OUT+ and
250 500 600 mV
0% Pre-emphasis
(2)
OUT−
ΔV
OD
Change in V
OD
between
−35 35 mV
Complementary States
V
OS
Offset Voltage
(3)
1.05 1.18 1.475 V
ΔV
OS
Change in V
OS
between
−35 35 mV
Complementary States
I
OS
Output Short Circuit Current OUT+ or OUT− Short to GND −60 −90 mA
C
OUT2
Output Capacitance OUT+ or OUT− to GND when TRI-STATE
®
5.5 pF
SUPPLY CURRENT (Static)
I
CC
Supply Current All inputs and outputs enabled and active,
terminated with differential load of 100Ω between 117 140 mA
OUT+ and OUT-, 0% pre-emphasis
I
CCZ
Supply Current - Power Down PWDN = L, 0% pre-emphasis
2.7 6 mA
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200 Mbps,
210 300 ps
Time measure between 20% and 80% of V
OD
.
(4)
t
HLT
Differential High to Low Transition
210 300 ps
Time
t
PLHD
Differential Low to High Use an alternating 1 and 0 pattern at 200 Mbps,
2.0 3.2 ns
Propagation Delay measure at 50% V
OD
between input to output.
t
PHLD
Differential High to Low
2.0 3.2 ns
Propagation Delay
t
SKD1
Pulse Skew |t
PLHD
–t
PHLD
|
(4)
25 80 ps
t
SKCC
Output Channel to Channel Skew Difference in propagation delay (t
PLHD
or t
PHLD
)
50 125 ps
among all output channels.
(4)
t
SKP
Part to Part Skew Common Edge, parts at same temp and V
CC
(4)
1.1 ns
t
JIT
Jitter (0% Pre-emphasis) RJ - Alternating 1 and 0 at 750 MHz
(6)
1.1 1.5 psrms
(5)
DJ - K28.5 Pattern, 1.5 Gbps
(7)
43 62 psp-p
TJ - PRBS 2
23
-1 Pattern, 1.5 Gbps
(8)
35 85 psp-p
t
ON
LVDS Output Enable Time Time from PWDN to OUT± change from TRI-STATE
300 ns
to active.
t
OFF
LVDS Output Disable Time Time from PWDN to OUT± change from active to
12 ns
TRI-STATE.
(3) Output offset voltage V
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
ID
= 500mV, 50%
duty cycle at 750MHz, t
r
= t
f
= 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V
ID
= 500mV, K28.5
pattern at 1.5 Gbps, t
r
= t
f
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = V
ID
= 500mV, 2
23
-1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50ps (20% to 80%).
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