Datasheet

DS90LV004

www.ti.com

SNLS190P –APRIL 2005–REVISED APRIL 2013

Pin Descriptions

Pin TQFP Pin

I/O, Type Description

Name Number

DIFFERENTIAL INPUTS

IN0+ 13 I, LVDS Channel 0 inverting and non-inverting differential inputs.

IN0− 14

IN1+ 15 I, LVDS Channel 1 inverting and non-inverting differential inputs.

IN1− 16

IN2+ 19 I, LVDS Channel 2 inverting and non-inverting differential inputs.

IN2− 20

IN3+ 21 I, LVDS Channel 3 inverting and non-inverting differential inputs.

IN3− 22

DIFFERENTIAL OUTPUTS

OUT0+ 48 O, LVDS Channel 0 inverting and non-inverting differential outputs.

(1)

OUT0− 47

OUT1+ 46 O, LVDS Channel 1 inverting and non-inverting differential outputs.

(1)

OUT1− 45

OUT2+ 42 O, LVDS Channel 2 inverting and non-inverting differential outputs.

(1)

OUT2− 41

OUT3+ 40 O, LVDS Channel 3 inverting and non-inverting differential outputs.

(1)

OUT3- 39

DIGITAL CONTROL INTERFACE

PWDN 12 I, LVTTL A logic low at PWDN activates the hardware power down mode.

PEM0 1 I, LVTTL Pre-emphasis Control Inputs (affects all Channels)

PEM1 2

POWER

3, 4, 5, 7, 10, 11, 27, 28, 29, 32, I, Power V

= 3.3V, ±5%

33, 34

GND 8, 9, 17, 18, 23, 24, 25, 26, 37, I, Power Ground reference for LVDS and CMOS circuitry.

38, 43, 44

N/C 6, 30, 31, 35, 36 No Connect

(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV004 device have

been optimized for point-to-point backplane and cable applications.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS90LV004