Datasheet

DS90CR483A, DS90CR484A
SNLS291A –APRIL 2008–REVISED APRIL 2013 www.ti.com
DS90CR484A Pin Descriptions—Channel Link Receiver
(1)
Pin Name I/O Description
RxINP I Positive LVDS differential data inputs.
RxINM I Negative LVDS differential data inputs.
RxOUT O TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are forced to a Low
state.
RxCLKP I Positive LVDS differential clock input.
RxCLKM I Negative LVDS differential clock input.
RxCLKOUT O TTL level clock output. The rising edge acts as data strobe.
PLLSEL I PLL range select. This pin should be tied to V
CC
for high-range. Tied to ground or NC will force the
PLL to low range only. Low range is 33 — 40 MHz. High range is 38 — 112 MHz.
(2)
DESKEW I Deskew / Oversampling “on/off” select. When using the Deskew / Oversample feature this pin
must be tied to V
CC
. Tieing this pin to ground disables this feature.
(2)
Deskew is only supported in
the DC Balance mode.
PD I TTL level input. When asserted (low input) the receiver outputs are Low.
(2)
V
CC
I Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins 6 and 77.
GND I Ground pins for TTL outputs and digital circuitry.
PLLV
CC
I Power supply for PLL circuitry.
PLLGND I Ground pin for PLL circuitry.
LVDSV
CC
I Power supply pin for LVDS inputs.
LVDSGND I Ground pins for LVDS inputs.
NC No Connect. Make NO Connection to these pins - leave open.
(1) These receivers have input fail-safe bias circuitry to ensure a stable receiver output for floating or terminated receiver inputs. Under test
conditions receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated
inputs, the outputs will remain in the last valid state.
(2) Inputs default to “low” when left open due to internal pull-down resistor.
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