Datasheet

DS90CR483A, DS90CR484A
www.ti.com SNLS291A –APRIL 2008–REVISED APRIL 2013
Results:
The DS90CR483A/DS90CR484A link was error free at 100MHz over 10 meters of 3M cable using pre-emphasis
and DC balance mode off.
DS90CR483A Pin Descriptions—Channel Link Transmitter
Pin Name I/O Description
TxIN I TTL level input.
(1)
.
TxOUTP O Positive LVDS differential data output.
TxOUTM O Negative LVDS differential data output.
TxCLKIN I TTL level clock input. The rising edge acts as data strobe.
TxCLKP O Positive LVDS differential clock output.
TxCLKM O Negative LVDS differential clock output.
PD I TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down.
(1)
.
PLLSEL I PLL range select. This pin should be tied to V
CC
for high-range. Tied to ground or NC will force the
PLL to low range. Low range is 33 — 40 MHz. High range is 38 — 112 MHz.
(1)
PRE I Pre-emphasis “level” select. Pre-emphasis is active when input is tied to V
CC
through external pull-
up resistor. Resistor value determines Pre-emphasis level (See Applications Information Section).
For normal LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to ground).
DS_OPT I Cable Deskew performed when TTL level input is low. No TxIN data is sampled during Deskew.
To perform Deskew function, input must be held low for a minimum of 4 clock cycles. The Deskew
operation is normally conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be performed at least once
when "DESKEW" is enabled.
(1)
Deskew is only supported in the DC Balance mode (BAL = High).
BAL I TTL level input. This pin was previously labeled as V
CC
, which enabled the DC Balance function.
But when tied low or left open, the DC Balance function is disabled. Please refer to (Figure 15
Figure 16) for LVDS data bit mapping respectively.
(1)
,
(2)
V
CC
I Power supply pins for TTL inputs and digital circuitry. Bypass not required on Pins 20 and 21.
GND I Ground pins for TTL inputs and digital circuitry.
PLLV
CC
I Power supply pin for PLL circuitry.
PLLGND I Ground pins for PLL circuitry.
LVDSV
CC
I Power supply pin for LVDS outputs.
LVDSGND I Ground pins for LVDS outputs.
NC No Connect. Make NO Connection to these pins - leave open.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The DS90CR484A is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483A and
deserialize the LVDS data according to the define bit mapping.
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