Datasheet
DS90CR287, DS90CR288A
SNLS056G –OCTOBER 1999–REVISED MARCH 2013
www.ti.com
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ
(1)
Max Units
CLHT CMOS/TTL Low-to-High Transition Time Figure 8 2 3.5 ns
CHLT CMOS/TTL High-to-Low Transition Time Figure 8 1.8 3.5 ns
RSPos0 Receiver Input Strobe Position for Bit 0 Figure 20 f = 85 MHz 0.49 0.84 1.19 ns
RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns
RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns
RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns
RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns
RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns
RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns
RSKM RxIN Skew Margin
(2)
Figure 21 f = 85 MHz 290 ps
RCOP RxCLK OUT Period Figure 11 11.76 T 50 ns
RCOH RxCLK OUT High Time Figure 11 f = 85 MHz 4 5 6.5 ns
RCOL RxCLK OUT Low Time Figure 11 3.5 5 6 ns
RSRC RxOUT Setup to RxCLK OUT Figure 11 3.5 ns
RHRC RxOUT Hold to RxCLK OUT Figure 11 3.5 ns
RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, V
CC
= 3.3V
(3)
Figure 13 5.5 7 9.5 ns
RPLLS Receiver Phase Lock Loop Set Figure 15 10 ms
RPDD Receiver Powerdown Delay Figure 18 1 μs
(1) Typical values are given for V
CC
= 3.3V and T
A
= +25°C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows
LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than 150 ps).
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
6 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR287 DS90CR288A