Datasheet

DS90CR287, DS90CR288A
www.ti.com SNLS056G –OCTOBER 1999–REVISED MARCH 2013
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ
(1)
Max Units
LLHT LVDS Low-to-High Transition Time Figure 7 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time Figure 7 0.75 1.5 ns
TCIT TxCLK IN Transition Time Figure 9 1.0 6.0 ns
TPPos0 Transmitter Output Pulse Position for Bit0 Figure 19 f = 85 MHz −0.20 0 0.20 ns
TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns
TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns
TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns
TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns
TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns
TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns
TCIP TxCLK IN Period Figure 10 11.76 T 50 ns
TCIH TxCLK IN High Time Figure 10 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time Figure 10 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN Figure 10 f = 85 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN Figure 10 0 ns
TCCD TxCLK IN to TxCLK OUT Delay Figure 12 T
A
= 25°C, V
CC
= 3.3V 3.8 6.3 ns
TPLLS Transmitter Phase Lock Loop Set Figure 14 10 ms
TPDD Transmitter Powerdown Delay Figure 17 100 ns
TJIT TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement) 2 ns
(1) Typical values are given for V
CC
= 3.3V and T
A
= +25°C.
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