Datasheet

DS90CR216A, DS90CR286A
www.ti.com SNLS043F –MAY 2000–REVISED FEBRUARY 2013
Figure 6. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay
Figure 7. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time
Figure 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A
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