Datasheet

DS90CR216A, DS90CR286A

SNLS043F –MAY 2000–REVISED FEBRUARY 2013

www.ti.com

Receiver Switching Characteristics

(1)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

RCOH RxCLK OUT High Time (Figure 5) f = 66 MHz 5.0 7.6 ns

RCOL RxCLK OUT Low Time (Figure 5) 5.0 6.3 ns

RSRC RxOUT Setup to RxCLK OUT (Figure 5) 4.5 7.3 ns

RHRC RxOUT Hold to RxCLK OUT (Figure 5) 4.0 6.3 ns

RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, V

= 3.3V

(3)

(Figure 6) 3.5 5.0 7.5 ns

RPLLS Receiver Phase Lock Loop Set (Figure 7) 10 ms

RPDD Receiver Power Down Delay (Figure 10) 1 μs

(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver

(RCCD). The total latency for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.

AC Timing Diagrams

Figure 3. “Worst Case” Test Pattern

Figure 4. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times

Figure 5. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times

Product Folder Links: DS90CR216A DS90CR286A