Datasheet

DS90CR216A, DS90CR286A
www.ti.com SNLS043F –MAY 2000–REVISED FEBRUARY 2013
Electrical Characteristics
(1)(2)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
RECEIVER SUPPLY CURRENT
ICCRW C
L
= 8 pF, Worst Case f = 33 MHz 49 65 mA
Pattern, DS90CR286A
f = 37.5 MHz 53 70 mA
Receiver Supply Current Worst Case
(Figure 3 Figure 4),
f = 66 MHz 81 105 mA
T
A
=−10°C to +70°C
ICCRW C
L
= 8 pF, Worst Case f = 40 MHz 53 70 mA
Pattern, DS90CR286A
Receiver Supply Current Worst Case
(Figure 3 Figure 4),
f = 66 MHz 81 105 mA
T
A
=−40°C to +85°C
ICCRW C
L
= 8 pF, Worst Case f = 33 MHz 49 55 mA
Pattern, DS90CR216A
f = 37.5 MHz 53 60 mA
Receiver Supply Current Worst Case
(Figure 3 Figure 4),
f = 66 MHz 78 90 mA
T
A
=−10°C to +70°C
ICCRW C
L
= 8 pF, Worst Case f = 40 MHz 53 60 mA
Pattern, DS90CR216A
Receiver Supply Current Worst Case
(Figure 3 Figure 4),
f = 66 MHz 78 90 mA
T
A
=−40°C to +85°C
ICCRZ Power Down = Low Receiver Outputs Stay
Receiver Supply Current Power Down 10 55 μA
Low during Power Down Mode
Receiver Switching Characteristics
(1)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 4) 2 5 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 4) 1.8 5 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 11, Figure 12) f = 40 MHz 1.0 1.4 2.15 ns
RSPos1 Receiver Input Strobe Position for Bit 1 4.5 5.0 5.8 ns
RSPos2 Receiver Input Strobe Position for Bit 2 8.1 8.5 9.15 ns
RSPos3 Receiver Input Strobe Position for Bit 3 11.6 11.9 12.6 ns
RSPos4 Receiver Input Strobe Position for Bit 4 15.1 15.6 16.3 ns
RSPos5 Receiver Input Strobe Position for Bit 5 18.8 19.2 19.9 ns
RSPos6 Receiver Input Strobe Position for Bit 6 22.5 22.9 23.6 ns
RSPos0 Receiver Input Strobe Position for Bit 0 f = 66 MHz
0.7 1.1 1.4 ns
(Figure 11, Figure 12)
RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns
RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns
RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns
RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns
RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns
RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns
RSKM f = 40 MHz 490 ps
RxIN Skew Margin
(2)
(Figure 13)
f = 66 MHz 400 ps
RCOP RxCLK OUT Period (Figure 5) 15 T 50 ns
RCOH RxCLK OUT High Time (Figure 5) f = 40 MHz 10.0 12.2 ns
RCOL RxCLK OUT Low Time (Figure 5) 10.0 11.0 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 5) 6.5 11.6 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 5) 6.0 11.6 ns
(1) Typical values are given for V
CC
= 3.3V and T
A
= +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
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Product Folder Links: DS90CR216A DS90CR286A