Datasheet

DS90CR285, DS90CR286
www.ti.com SNLS130C –MARCH 1999–REVISED MARCH 2013
Figure 14. DS90CR285 (Transmitter) Phase Lock Loop Set Time
Figure 15. DS90CR286 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in Once Clock Cycle
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS90CR285 DS90CR286