Datasheet

DS90CR285, DS90CR286
www.ti.com SNLS130C –MARCH 1999–REVISED MARCH 2013
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 6) 0.5 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 6) 0.5 1.5 ns
TCIT TxCLK IN Transition Time (Figure 8) 5 ns
TCCS TxOUT Channel-to-Channel Skew (Figure 9) 250 ps
TPPos0 Transmitter Output Pulse Position for Bit0 f = 40 MHz −0.4 0 0.4 ns
(1)
(Figure 20)
TPPos1 Transmitter Output Pulse Position for Bit1 3.1 3.3 4.0 ns
TPPos2 Transmitter Output Pulse Position for Bit2 6.5 6.8 7.6 ns
TPPos3 Transmitter Output Pulse Position for Bit3 10.2 10.4 11.0 ns
TPPos4 Transmitter Output Pulse Position for Bit4 13.7 13.9 14.6 ns
TPPos5 Transmitter Output Pulse Position for Bit5 17.3 17.6 18.2 ns
TPPos6 Transmitter Output Pulse Position for Bit6 21.0 21.2 21.8 ns
TPPos0 Transmitter Output Pulse Position for Bit0 f = 66 MHz −0.4 0 0.3 ns
(2)
(Figure 20)
TPPos1 Transmitter Output Pulse Position for Bit1 1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit2 4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit3 6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit4 8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit5 10.6 11.0 11.3 ns
TPPos6 Transmitter Output Pulse Position for Bit6 12.8 13.2 13.5 ns
TCIP TxCLK IN Period (Figure 10 ) 15 T 50 ns
TCIH TxCLK IN High Time (Figure 10) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 10) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (Figure 10) 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 10) 0 ns
TCCD TxCLK IN to TxCLK OUT Delay @ 25°C,V
CC
=3.3V (Figure 12) 3 3.7 5.5 ns
TPLLS Transmitter Phase Lock Loop Set (Figure 14) 10 ms
TPDD Transmitter Powerdown Delay (Figure 18) 100 ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 7) 2.2 5.0 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 7) 2.2 5.0 ns
RSPos0 Receiver Input Strobe Position for Bit 0
(1)
(Figure 21) f = 40 MHz 1.0 1.4 2.15 ns
RSPos1 Receiver Input Strobe Position for Bit 1 4.5 5.0 5.8 ns
RSPos2 Receiver Input Strobe Position for Bit 2 8.1 8.5 9.15 ns
RSPos3 Receiver Input Strobe Position for Bit 3 11.6 11.9 12.6 ns
RSPos4 Receiver Input Strobe Position for Bit 4 15.1 15.6 16.3 ns
RSPos5 Receiver Input Strobe Position for Bit 5 18.8 19.2 19.9 ns
RSPos6 Receiver Input Strobe Position for Bit 6 22.5 22.9 23.6 ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
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