Datasheet

DS90CR217
SNLS226A –OCTOBER 2006–REVISED FEBRUARY 2013 www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
s
V
OS
Offset Voltage
(1)
1.12 1.25 1.37 V
5 5
ΔV
OS
Change in V
OS
between Complimentary Output
35 mV
States
I
OS
Output Short Circuit Current V
OUT
= 0V, R
L
= 100Ω −3.5 −5 mA
I
OZ
Output TRI-STATE Current PWR DWN = 0V, V
OUT
= 0V or V
CC
±1 ±10 μA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current Worst Case (with R
L
= 100Ω, f = 33 MHz 28 42 mA
Loads) C
L
= 5 pF,
f = 40 MHz 29 47 mA
Worst Case Pattern
f = 66 MHz 34 52 mA
(Figure 3 and Figure 4)
f = 85 MHz 39 57 mA
I
CCTZ
Transmitter Supply Current Power Down PWR DWN = Low
Driver Outputs in TRI-STATE 10 55 μA
under Powerdown Mode
(1) V
OS
previously referred as V
CM
.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 4) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 4) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (Figure 5) 1.0 6.0 ns
TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 12) f = 85 MHz −0.20 0 0.20 ns
TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns
TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns
TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns
TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns
TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns
TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns
TCIP TxCLK IN Period (Figure 7) 11.76 T 50 ns
TCIH TxCLK IN High Time (Figure 7) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 7) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (Figure 7) f = 85 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 7) 0 ns
TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, V
CC
= 3.3V (Figure 8) 3.8 6.3 ns
TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms
TPDD Transmitter Powerdown Delay (Figure 11) 100 ns
TJIT TxCLK IN Cycle-to-Cycle Jitter 2 ns
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