Datasheet

DS90CR215, DS90CR216
www.ti.com SNLS129D –MARCH 1999–REVISED APRIL 2013
Figure 15. DS9OCR216 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in Once Clock Cycle
Figure 17. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR215)
Figure 18. Transmitter Powerdown Delay
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