Datasheet

DS90CR215, DS90CR216
SNLS129D –MARCH 1999–REVISED APRIL 2013 www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
s
V
TH
Differential Input High Threshold V
CM
= +1.2V +100 mV
V
TL
Differential Input Low Threshold −100 mV
I
IN
Input Current V
IN
= +2.4V, V
CC
= 3.6V ±10 μA
V
IN
= 0V, V
CC
= 3.6V ±10 μA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current Worst Case (with R
L
= 100Ω, f = 32.5 MHz 31 45 mA
Loads) C
L
= 5 pF,
f = 37.5 MHz 32 50 mA
Worst Case Pattern
f = 66 MHz 37 55 mA
(Figure 5 Figure 6),
T
A
= −10°C to +70°C
R
L
= 100Ω, f = 40 MHz 38 51 mA
C
L
= 5 pF,
f = 66 MHz 42 55 mA
Worst Case Pattern
(Figure 5 Figure 6),
T
A
= −40°C to +85°C
I
CCTZ
Transmitter Supply Current Power Down PWR DWN = Low 10 55 μA
Driver Outputs in TRI-STATE
under Powerdown Mode
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current Worst Case C
L
= 8 pF, f = 32.5 MHz 49 65 mA
Worst Case Pattern
f = 37.5 MHz 53 70 mA
(Figure 5 Figure 7), T
f = 66 MHz 78 105 mA
A
= −10°C to +70°C
C
L
= 8 pF, f = 40 MHz 55 82 mA
Worst Case Pattern
f = 66 MHz 78 105 mA
(Figure 5 Figure 7),
T
A
= −40°C to +85°C
I
CCRZ
Receiver Supply Current Power Down PWR DWN = Low 10 55 μA
Receiver Outputs Stay Low during
Powerdown Mode
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 6) 0.5 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 6) 0.5 1.5 ns
TCIT TxCLK IN Transition Time (Figure 8) 5 ns
TCCS TxOUT Channel-to-Channel Skew (Figure 9) 250 ps
TPPos0 Transmitter Output Pulse Position for Bit0
(1)
f = 40 MHz −0.4 0 0.4 ns
(Figure 20)
TPPos1 Transmitter Output Pulse Position for Bit1 3.1 3.3 4.0 ns
TPPos2 Transmitter Output Pulse Position for Bit2 6.5 6.8 7.6 ns
TPPos3 Transmitter Output Pulse Position for Bit3 10.2 10.4 11.0 ns
TPPos4 Transmitter Output Pulse Position for Bit4 13.7 13.9 14.6 ns
TPPos5 Transmitter Output Pulse Position for Bit5 17.3 17.6 18.2 ns
TPPos6 Transmitter Output Pulse Position for Bit6 21.0 21.2 21.8 ns
(1) The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
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