Datasheet

DS90CR215, DS90CR216
www.ti.com SNLS129D –MARCH 1999–REVISED APRIL 2013
DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS
21-Bit Channel Link - 66 MHz
Check for Samples: DS90CR215, DS90CR216
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FEATURES
DESCRIPTION
The DS90CR215 transmitter converts 21 bits of
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• Single +3.3V Supply
CMOS/TTL data into three LVDS (Low Voltage
• Chipset (Tx + Rx) Power Consumption <250
Differential Signaling) data streams. A phase-locked
mW (typ)
transmit clock is transmitted in parallel with the data
• Power-down Mode (<0.5 mW total)
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
• Up to 173 Megabytes/sec Bandwidth
transmitted. The DS90CR216 receiver converts the
• Up to 1.386 Gbps Data Throughput
LVDS data streams back into 21 bits of CMOS/TTL
• Narrow Bus Reduces Cable Size
data. At a transmit clock frequency of 66 MHz, 21 bits
of TTL data are transmitted at a rate of 462 Mbps per
• 290 mV Swing LVDS Devices for Low EMI
LVDS data channel. Using a 66 MHz clock, the data
• +1V Common Mode Range (Around +1.2V)
throughput is 1.386 Gbit/s (173 Mbytes/s).
• PLL Requires No External Components
The multiplexing of the data lines provides a
• Low Profile 48-Lead TSSOP Package
substantial cable reduction. Long distance parallel
• Rising Edge Data Strobe
single-ended buses typically require a ground wire
per active signal (and have very limited noise
• Compatible with TIA/EIA-644 LVDS Standard
rejection capability). Thus, for a 21-bit wide data and
• ESD Rating > 7 kV
one clock, up to 44 conductors are required. With the
• Operating Temperature: −40°C to +85°C
Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required
cable width, which provides a system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements due to the cables'
smaller form factor.
The 21 CMOS/TTL inputs can support a variety of
signal combinations. For example, five 4-bit nibbles
plus 1 control, or two 9-bit (byte + parity) and 3
control.
Block Diagram
Figure 1. DS90CR215 Figure 2. DS90CR216 - Improved AC Specifications
48-Lead TSSOP See Package Number DGG0048A
See Package Number DGG0048A Recommended Alternative Device
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PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.