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AC Timing Diagrams (Continued)

Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 8:

Figures 1, 2

show a falling edge data strobe (TxCLK IN/RxCLK OUT).

Note 9: Recommended pin to signal mapping. Customer may choose to define differently.

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FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9)

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FIGURE 3. DS90C383 (Transmitter) LVDS Output Load and Transition Times

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FIGURE 4. DS90CF384 (Receiver) CMOS/TTL Output Load and Transition Times

DS90C383/DS90CF384