Datasheet

Electrical Characteristics (Continued)
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and ∆V
OD
).
Note 4: V
OS
previously referred as V
CM
.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time
(Figure 3 ) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time
(Figure 3 ) 0.75 1.5 ns
TCIT TxCLK IN Transition Time
(Figure 4 ) 5ns
TCCS TxOUT Channel-to-Channel Skew
(Figure 5 ) 250 ps
TPPos0 Transmitter Output Pulse Position for Bit 0
(Figure 12 ) f = 65 MHz −0.4 0 0.3 ps
TPPos1 Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns
TCIP TxCLK IN Period
(Figure 6) 15 T 50 ns
TCIH TxCLK IN High Time
(Figure 6) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time
(Figure 6) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN
(Figure 6) f = 65 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN
(Figure 6) 0ns
TCCD TxCLK IN to TxCLK OUT Delay 25˚C, V
CC
= 3.3V (Figure 7 ) 3 5.5 ns
TPLLS Transmitter Phase Lock Loop Set
(Figure 8 ) 10 ms
TPDD Transmitter Power Down Delay
(Figure 11) 100 ns
AC Timing Diagrams
DS100033-4
FIGURE 1. “Worst Case” Test Pattern
DS90CF383
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