DS90CF383 DS90CF383 +3.
DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link— 65 MHz General Description Features The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
DS90CF383 Absolute Maximum Ratings (Note 1) Package Derating: DS90CF383 ESD Rating (HBM, 1.5 kΩ, 100 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 12.5 mW/˚C above +25˚C > 7 kV Recommended Operating Conditions Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.
(Continued) Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Note 4: VOS previously referred as VCM.
DS90CF383 AC Timing Diagrams (Continued) DS100033-5 FIGURE 2. “16 Grayscale” Test Pattern (Notes 5, 6, 7, 8) Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
DS90CF383 AC Timing Diagrams (Continued) DS100033-9 Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low → High Edge FIGURE 5. DS90CF383 (Transmitter) Channel-to-Channel Skew DS100033-10 FIGURE 6. DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) DS100033-12 FIGURE 7. DS90CF383 (Transmitter) Clock In to Clock Out Delay 5 www.national.
DS90CF383 AC Timing Diagrams (Continued) DS100033-14 FIGURE 8. DS90CF383 (Transmitter) Phase Lock Loop Set Time DS100033-16 FIGURE 9. Seven Bits of LVDS in Once Clock Cycle DS100033-17 FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.
DS90CF383 AC Timing Diagrams (Continued) DS100033-18 FIGURE 11. Transmitter Power Down Delay DS100033-26 FIGURE 12. Transmitter LVDS Output Pulse Position Measurement DS90CF383 Pin Description — FPD Link Transmitter I/O No. TxIN Pin Name I 28 Description TxOUT+ O 4 Positive LVDS differentiaI data output. TxOUT− O 4 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
DS90CF383 DS90CF383 Pin Description — FPD Link Transmitter Pin Name I/O No. I 4 GND (Continued) Description Ground pins for TTL inputs. PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. Applications Information and receiver devices. This change may enable the removal of a 5V supply from the system, and power may be supplied from an existing 3V power source.
inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF383MTD NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
