Datasheet

DS90CF383B
SNLS178E –JULY 2004–REVISED APRIL 2013 www.ti.com
DS90CF383B PIN DESCRIPTIONS — FPD LINK TRANSMITTER
Pin Name I/O No. Description
TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME and
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+ O 4 Positive LVDS differential data output.
TxOUT− O 4 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
See Applications Information.
V
CC
I 4 Power supply pins for TTL inputs.
GND I 5 Ground pins for TTL inputs.
PLL V
CC
I 1 Power supply pin for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS V
CC
I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.
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