Datasheet

DS90CF383B
www.ti.com SNLS178E –JULY 2004–REVISED APRIL 2013
AC Timing Diagrams
Figure 1. “Worst Case” Test Pattern
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Recommended pin to signal mapping. Customer may choose to define differently.
Figure 2. “16 Grayscale” Test Pattern
Figure 3. DS90CF383B (Transmitter) LVDS Output Load
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