Datasheet

DS90CF366, DS90CF386
SNLS055I –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com
Figure 8. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay
Figure 9. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time
Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386
Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF366
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