Datasheet

DS90CF366, DS90CF386
SNLS055I –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern (DS90CF386)
4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF366 DS90CF386